View RD38F4460LVY_6932131.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel strataflash ? wireless memory system (lv18 scsp) 1024-mbit lvx family with lpsdram datasheet product features intel strataflash ? wireless memory system (lv18 scsp) with low-power sdram (lvx family) offers a variety of high performance code segment, large embedded data segment, and low-power sdram combinations in a common package on 0.13 m etox? viii flash technology. the lvx family integrates up to two code segment flash dies, two data segment flash dies, and two low-power sdram dies or one sram die in a common x16d performance ballout. device memory architecture ? flash die density: 128-, 256-mbit ? lpsdram die density: 128-, 256-mbit ? top or bottom parameter flash configuration device voltage ? core: v cc = 1.8 v (typ.) ? i/o: v ccq = 1.8 v (typ.) device common performance ? buffered efp: 5 s / byte (typ.) per die ? buffer program: 7 s / byte (typ.) per die ? concurrent buffered efp: 6.4-mbps effective with 4 flash dies device common architecture ? asymmetrical blocking structure ? 16-kword parameter blocks (top or bottom); 64-kword main blocks ? zero-latency block locking ? absolute write protection with block lock down using f-vpp and f-wp# device packaging ? 103 active balls; 9 x 12 ball matrix ? area: 9 x 11 mm to 11 x 11 mm ? height: 1.4 mm sdram architecture and performance ? clock rate: 105 mhz ? four internal banks ? burst length: 1, 2, 4, 8, or full page code segment flash read performance ? 85 ns initial access ? 25 ns asynchronous page read ? 14 ns synchronous read (t chqv ) ? 54 mhz (max.) clk data segment flash performance ? 170 ns initial access ? 55 ns asynchronous page read code segment flash architecture ? hardware read-while-write/erase ? multiple 8-mbit / 16-mbit partition sizes ? 2-kbit one-time-programmable protection register data segment flash architecture ? software read-while-write/erase ? single partition size die flash software ?intel ? fdi, intel ? psm, and intel ? vfm ? common flash interface ? basic/extended command set quality and reliability ? extended temperature: ? 25 c to +85 c ? minimum 100 k flash block erase cycle ? 0.13 m etox ? viii flash technology 300945-006 october 2004 notice: this document contains information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design. .com .com .com .com 4 .com u datasheet
2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuc lear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. the intel strataflash ? wireless memory system (lv18 scsp) 1024-mbit lvx family with low-power sdram may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are availabl e on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2004, intel corporation. .com .com .com .com .com 4 .com u datasheet
datasheet 3 contents contents 1.0 introduction ............................................................................................................................... 7 1.1 nomenclature ................................................................................................................ .......7 1.2 acronyms .................................................................................................................... ..........8 1.3 conventions................................................................................................................. .........9 2.0 functional overview ............................................................................................................11 2.1 product description ......................................................................................................... ...11 2.2 unique product features....................................................................................................1 3 2.3 product configurations and memory partitioning ...............................................................13 2.4 memory map.................................................................................................................. .....15 3.0 package information ............................................................................................................21 4.0 ballout and signal descriptions ......................................................................................23 4.1 signal ballout.............................................................................................................. ........23 4.2 signal descriptions ......................................................................................................... ....24 5.0 maximum ratings and operating conditions ...........................................................27 5.1 absolute maximum ratings ................................................................................................27 5.2 operating conditions ........................................................................................................ ..28 6.0 electrical specifications .....................................................................................................29 6.1 dc voltage and current characteristics.............................................................................29 7.0 ac characteristics ................................................................................................................31 7.1 device ac test conditions .................................................................................................31 7.2 capacitance................................................................................................................. .......31 7.3 flash ac read operations.................................................................................................31 7.4 flash ac write operations .................................................................................................32 7.5 lpsdram ac characteristics............................................................................................32 8.0 power and reset specifications .....................................................................................34 9.0 operations overview ...........................................................................................................34 9.1 bus operations .............................................................................................................. .....34 .com .com .com .com .com 4 .com u datasheet
contents 4 datasheet 10.0 flash read operations ....................................................................................................... 40 11.0 flash program operations ................................................................................................ 40 12.0 flash erase operations ...................................................................................................... 40 13.0 flash suspend and resume operations ..................................................................... 40 14.0 flash block locking and unlocking operations ...................................................... 40 15.0 flash protection register operations .......................................................................... 40 16.0 flash configuration operations ...................................................................................... 40 17.0 flash dual operation considerations .......................................................................... 41 18.0 lpsdram operations ......................................................................................................... 41 18.1 lpsdram power-up sequence and initialization .............................................................. 41 18.2 lpsdram mode register .................................................................................................. 41 18.3 extended mode register .................................................................................................... 4 2 18.4 lpsdram commands and operations ............................................................................. 43 18.4.1 lpsdram no operation / device deselect .......................................................... 43 18.4.1.1 device deselect (nop).......................................................................... 43 18.4.1.2 no operation (nop) .............................................................................. 43 18.4.2 lpsdram active................................................................................................... 43 18.4.3 lpsdram read.................................................................................................... 44 18.4.4 lpsdram write .................................................................................................... 44 18.4.5 lpsdram power-down........................................................................................ 45 18.4.6 lpsdram deep power-down .............................................................................. 45 18.4.7 lpsdram clock suspend .................................................................................... 45 18.4.8 lpsdram precharge............................................................................................ 46 18.4.9 lpsdram auto precharge ................................................................................... 46 18.4.10 lpsdram concurrent auto precharge................................................................. 46 18.4.11 lpsdram burst terminate................................................................................... 54 18.4.12 lpsdram auto refresh ....................................................................................... 54 18.4.13 lpsdram self refresh......................................................................................... 54 appendix a write state machine .......................................................................................... 55 appendix b common flash interface ................................................................................ 55 appendix c flash flowcharts ............................................................................................... 55 appendix d additional information ..................................................................................... 56 appendix e ordering information ....................................................................................... 57 .com .com .com .com .com 4 .com u datasheet
datasheet 5 contents revision history date revision description february, 2004 -001 initial release. february, 2004 -002 corrected information in the memory map table, code and data segments, bottom parameter. april, 2004 -003 corrected errors in table 1 and table 26. the package dimension of part rd48f4444lvybb0 rd48f4444lvytb0 now reads 11x11x1.4 instead of 9x11x1.4. june, 2004 -004 updated table 1 and table 26. added line item RD38F4460LVYgb0. added g as an option to figure 29 - ordering information. added figure 6, a top-top memory map diagram. added top/top configuration feature to the title page ?product features?. july, 2004 -005 added the mechanical specification diagram, figure 5 for the 11x11x1.4 mm option. october, 2004 -006 added line items 256l18/256v18/256sd, 256l18/256l18/ 256v18/256sd, and 256l18/256v18/256v18/256sd to the following tables: * table 1 ?available product ordering information for the lvx family with lpsdram? on page 12 * table 26 ?lvx family with lpsdram: available product ordering information? on page 57. . .com .com .com .com .com 4 .com u datasheet
contents 6 datasheet .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 7 1.0 introduction this document provides preliminary information about the intel strataflash ? wireless memory system (lv18 scsp) with low-power sdram (lvx family). this document describes the flash dies used in the code and large embedded data segments and the features, operations, and specifications within the subsystem. also described in this document are the lpsdram characteristics and operations. the intent of this document is to provide information where these scsp products differ from the intel strataflash ? wireless memory system (lv18) datasheet. refer to the latest revision of the intel strataflash ? wireless memory system datasheet (order number 253854) for flash product details not included in this document. 1.1 nomenclature 1.8 v core voltage range of 1.7 v ? 1.95 v 1.8 v i/o voltage range of 1.7 v ? 1.95 v asserted signal with logical voltage level v il , or enabled deasserted signal with logical voltage level v ih , or disabled high-z tri-stated or high impedance low-z driven non-array reads flash reads which return flash device identifier, cfi query, protection register and status register information program an operation to write data to the flash array write bus cycle operation at the inputs of the flash die, in which a command or data are sent to the flash array block group of cells, bits, bytes or words within the flash memory array that get erased with one erase instruction parameter block any 16-kword flash array block. main block any 64-kword flash array block. top parameter previously referred to as a top-boot device, a device with flash parameter partition located at the highest physical address of its memory map for processor system boot up. bottom parameter previously referred to as a bottom-boot device, a device with flash parameter partition located at the lowest physical address of its memory map for processor system boot up. bottom-top parameter scsp device configuration of two flash dies in the same segment arranged with the parameter partitions located at the lowest and highest physical address of its memory map. .com .com .com .com .com 4 .com u datasheet
lvx family 8 datasheet partition a group of flash blocks that shares common status register read state. parameter partition a flash partition containing parameter and main blocks. main partition a flash partition containing only main blocks. die individual physical flash or ram die used in a scsp memory subsystem device segment a section of the scsp memory subsystem divided for different operating characteristics. the scsp memory subsystem has three segments: a code segment, a data segment, and an xram segment. code segment a segment that contains one or two flash memory dies optimized for fast code or data reads. each die features multi-partitions synchronous read-while-write or burst read-while-erase capability. data segment a segment contains one or two flash memory dies optimized for large embedded data. each die feature single-partition asynchronous read, write, and erase operations. xram segment a segment contains one or two xram memory dies. the xram combinations could include sram, psram, or lpsdram. subsystem a stacked memory integration concept made up of multiple memory dies arranged in code, data, and xram segments. device a specific stacked flash + xram memory density configuration combination within the lvx product family. 1.2 acronyms aps automatic power savings buffered efp buffered enhanced factory programming cfi common flash interface cr configuration register cui command user interface du do not use etox eprom tunnel oxide otp one-time programmable plr protection lock register pr protection register rcr read configuration register rfu reserved for future use (all unused active signals in a package ballout) .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 9 rwe read-while-erase rww read-while-write scsp stacked chip scale package sr status register srd status register data wsm write state machine 1.3 conventions 0x hexadecimal number prefix 0b binary number prefix a5 denotes one element of a signal group membership, in this case address bit 5. adv# a name without a prefix denotes a global signal of the device; for example, address valid is global because there is no die specific reference. bit binary unit, valid range [0, 1] byte eight bits, valid range [0x00 - 0xff] clear logical zero (0) dq[15:0] denotes a group of similarly named signals, such as data bus. f[3:1]-ce#, f[2:1]-oe# this is the method used to refer to more than one chip-enable or output enable at the same time. when each die is refer to individually, the reference will be f1-ce# and f1-oe# (for die #1), f2-ce# and f2-oe# (for die #2), and f3-ce# (for die #3), unless noted otherwise. ?f? denotes the flash specific signal and ?ce#? is the root signal name of the flash die chip-enable. other notation includes: ?s? to denote sram, ?p? to denote psram, ?d? to denote lpsdram, and ?r? to denote common ram type signal names. k (noun) 1000 (units) kb 1024 bits kb 1024 bytes kbit 1024 bits kbyte 1024 bytes (8,192 bits) kword 1024 words (16,384 bits) mbit 1,048,576 bits mbyte 1,048,576 bytes (8,388,608 bits) .com .com .com .com .com 4 .com u datasheet
lvx family 10 datasheet mword 1,048,576 words (16,777,216 bits) m (noun) 1 million mb 1,048,576 bits mb 1,048,576 bytes set logical one (1) sr[4] denotes an individual flash status register bit, in this case bit 4 of sr[7:0]. vcc signal or voltage connection v cc signal or voltage level word two bytes or sixteen bits, valid range [0x0000 - 0xffff] .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 11 2.0 functional overview this section provides an overview of the features and capabilities of intel strataflash ? wireless memory system (lv18 scsp) with low-power sdram lvx family; hereafter in this document, this device is called the lvx family with lpsdram device. 2.1 product description the lvx family with lpsdram device incorporates flash dies used as code segment flash die and large embedded data segment flash die, along with lpsdram for a high performance, cost- effective high density solution. this stacked device utilizes the latest intel strataflash ? wireless memory system on 0.13 m etox? viii process technology. the code segment flash is a high performance, multi-partition, synchronous burst-mode read- while-write (rww) or read-while-erase (rwe), while the large embedded data segment is a cost efficient, single partition, asynchronous memory die. the package for this device is available in a x16d performance ballout, supporting flash-only or flash with lpsdram stacked memory combinations. the intel ? scsp package in a x16d performance ballout with a 0.8 mm ball pitch, 9 x 12 active ball matrix supports a memory subsystem up to 105 mhz on a x16-bit bus width. see figure 1, ?lvx family with lpsdram device block diagram? on page 11 . figure 1. lvx family with lpsdram device block diagram xram segment lvx family flash die #1 (128- or 256-mbit) flash (code/data) segment flash die #3 (128- or 256-mbit) flash die #2 (128- or 256-mbit) flash die #4 (128- or 256-mbit) r-vcc d-cas# d-ba[1:0] r-clk d-ras# d-cke f-rst# we# f-clk a[max:min] dq[15:0] f3-ce# f1-ce# f-wp1# f-wp2# adv# wait oe# d-dm1 / r-ub# f-vcc f-vpp vccq vss f4-ce# f2-ce# s-cs2 s-cs1# s-vcc d-dm0 / r-lb# r2-cs# sram die #1 (8-mbit) lpsdram die #2 (128/256-mbit) lpsdram die #1 (128/256-mbit) r1-cs# .com .com .com .com .com 4 .com u datasheet
lvx family 12 datasheet note: you can request the stacked flash + xram combinations based on memory die options shown in figure 1 . for current available flash + xram combinations, refer to ta bl e 1 . the lvx family with lpsdram device consists of a 1.8 v flash core device (f-v cc ) with 1.8 v and 3.0 v i/o options. the device is available with at least one flash die per code segment and/or one flash die per data segment. however, it has a maximum of two flash dies per code or data segments. see table 2, ?lv flash code and data die (f-ce#) stacked configuration? on page 15 for possible combinations. designed for low-voltage systems, the lvx supports read operations with f-v cc at 1.8 v, and erase and program operations with f-v pp at 1.8 v. buffered enhanced factory programming (buffered efp) provides the fastest flash array programming performance, with elevated f-v pp at 9.0 v to increase factory throughput. with f-v pp at 1.8 v, f-v cc and f-v cc can be tied together for a simple, ultra-low-power design. in addition to voltage flexibility, a dedicated f-v pp connection provides complete data protection when f-v pp v pplk . the intel strataflash ? wireless memory system provides data security through its individual zero- latency block lock capability. each memory block can be unlocked, locked, or locked-down by hardware or software control. individualized f-ce# control allows the user to manage which flash die is asserted, furthering the flexibility of power management while controlling data integrity per segment with f-wp#. the f[2:1]-oe# in lvx products with a x16d performance ballout ballout are common internally. table 1 lists the available lvx product family devices. if the product combinations you are seeking are not listed, the combination is not available at this time and you will need to contact your local intel representative for details. . table 1. available product ordering information for the lvx family with lpsdram i/o voltage (v) flash density (mbit) and family ram density (mbit) and ram type package part number notes size (mm) ballout name ball type 1.8 256 l18 + 256 l18 + 256 v18 + 256 v18 ?11x11x1.4 x16d (103 ball) scsp leaded rd48f4444lvybb0 rd48f4444lvytb0 256 l18 + 256 v18 128 sdram 9x11x1.4 x16d (103 ball) scsp leaded RD38F4460LVYbb0 RD38F4460LVYtb0 RD38F4460LVYgb0 1 256 l18 + 256 l18 + 256 v18 128 sdram 9x11x1.4 x16d (103 ball) scsp leaded rd58f0012lvybb0 rd58f0012lvytb0 2 256 l18 + 256 v18 + 256 v18 128 sdram 9x11x1.4 x16d (103 ball) scsp leaded rd58f0016lvybb0 rd58f0016lvytb0 2 notes: 1. for the ?custom? line item RD38F4460LVYgb0, the ?g? designate the f-ce# parameter configuration where f1-ce# = top parameter and f2 -ce# = top parameter. see table 2 for details. 2. 58fxxxx nomenclature is used when the stacked de vice has greater than three flash + ram dies. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 13 2.2 unique product features the code segment of the lvx includes the following enhanced features unless specifically noted otherwise: 64 unique (intel pre-programmed) identifier bits and 2,112 user-programmable otp bits for each code segment flash die. traditional write, erase, and burst-mode read capabilities of intel ? wireless flash memory (w18). simultaneous rww/rwe operations, enabling a burst read operation in one partition with simultaneous program or erase operations in other partitions. burst-read across partition boundaries, but not across segment dies within the subsystem. user application code responsible for ensuring that burst-mode reads do not cross into a partition that is in program or erase mode. the embedded data segment includes the following features unless specifically noted otherwise: high density offerings of up to 512 mbits are designated specifically for large embedded data. single partition asynchronous page-mode read operation, allowing for a cost-effective ideal storage format. read-while-write or read-while-erase operations can be accomplished with software through program suspend and erase suspend operations. 2.3 product configurations and memory partitioning the first flash die, by default is the first code segment flash die, which is a fast, execute-in-place (xip) solution that is ideally suited toward an instruction fetch application. this portion is the user selected parameter configuration option, where the density can be made up of 128-mbit dies or 256-mbit dies, each containing one parameter partition and several main partitions.the parameter partition contains four 16-kword parameter blocks and seven 64-kword main blocks; all main partitions consist of eight 64-kword main blocks. the large embedded data die segment is a single partition asynchronous page-mode read device that is available in variations of 128-mbit dies or 256-mbit dies. the single partition is made up of four 16-kword parameter blocks and 64-kword main blocks. the data segment flash die parameter configuration will always be the opposite of the code segment flash die parameter configuration. see table 2, ?lv flash code and data die (f-ce#) stacked configuration? on page 15 for examples of configuration options. users have the choice of selecting either a top or a bottom parameter configuration for the code die segment. depending on the choice of configuration, the data die(s) in the lvx device will be parametrically opposed. for instance, if the user selects top parameter configuration for the code die, the data die in the package will be configured as bottom parameter configuration, and vice- versa. this ensures the largest number of contiguous main block addresses for software efficiency. the xram segment can consist of up to two low-power sdram (lpsdram) dies. the lpsdram can be either a 128-mbit or a 256-mbit die. for the code segment, partition configurations are as follows: 128-mbit flash die partitions are 8 mbits. 256-mbit flash die partitions are 16 mbits. minimum code + data density combination is 384 mbits. .com .com .com .com .com 4 .com u datasheet
lvx family 14 datasheet figure 2. top parameter configurations figure 3. bottom para meter configurations 1 code + 1 data data (bottom) code (top) parameter blocks main blocks parameter blocks data (top) 1 code + 2 data code (top) data (bottom) code (top) 2 code + 1 data code (top) data (bottom) 2 code + 2 data code (top) code (bottom) data (top) data (bottom) data (top) code (bottom) data (top) data (bottom) code (top) code (bottom) data (bottom) data (top) code (bottom) code (bottom) data (top) code (bottom) parameter blocks main blocks parameter blocks 1 code + 1 data 1 code + 2 data 2 code + 1 data 2 code + 2 data .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 15 table 2 shows an example of the memory map and partitioning information for combinations with up to four flash dies in the lvx scsp family with synchronous lpsdram. top parameter configuration. for two flash dies, flash die #1 (with f1-ce# as its chip enable) is configured as top parameter. flash die #2 (with f2-ce# as its chip enable) is configured as bottom parameter. bottom parameter configuration. for two flash dies, flash die #1 (with f1-ce# as its chip enable) is configured as bottom parameter. flash die #2 (with f2-ce# as its chip enable) is configured as top parameter. top-top parameter configuration is a custom option, where all flash dies within the stacked device has the same parameter configuration. in this case, all dies are top configured. 2.4 memory map the lvx family with lpsdram device is available in several density and parameter configurations. the memory map is based on the stacking of individual 128- and 256-mbit flash die density options. the memory map shows individu al flash die configurations and block/partition allocations. see the following tables for further information: table 3, ?code-data (top parameter) scsp memory map and partitioning? on page 16 table 4, ?code-data (bottom parameter) scsp memory map and partitioning? on page 17 table 5, ?code-data (top - top parameter) scsp memory map and partitioning? on page 18 table 6, ?code-code-data (top parameter) scsp memory map and partitioning? on page 19 table 7, ?code-code-data (bottom parameter) scsp memory map and partitioning? on page 20 table 2. lv flash code and data die (f-ce#) stacked configuration die stack configuration code segment data segment 1st flash code die (user selected) 2nd flash code die 1st flash data die 2nd flash data die top parameter code + data f1-ce# (top) f2-ce# (bottom) ? ? code + data + data f1-ce# (top) f2-ce# (top) f3-ce# (bottom) ? code + code + data f1-ce# (top) f2-ce# (top) f3-ce# (bottom) ? code + code + data + data f1-ce# (top) f2-ce# (bottom) f3-ce# (top) f4-ce# (bottom) bottom parameter code + data f1-ce# (bottom) f2-ce# (top) ? ? code + data + data f1-ce# (bottom) f2-ce# (bottom) f3-ce# (top) ? code + code + data f1-ce# (bottom) f2-ce# (bottom) f3-ce# (top) ? code + code + data + data f1-ce# (bottom) f2-ce# (top) f3-ce# (bottom) f4-ce# (top) top-top parameter (custom) code + data f1-ce# (top) f2-ce# (top) ? ? code + data + data f1-ce# (top) f2-ce# (top) f3-ce# (top) ? code + code + data f1-ce# (top) f2-ce# (top) f3-ce# (top) ? code + code + data + data f1-ce# (top) f2-ce# (top) f3-ce# (top) f4-ce# (top) .com .com .com .com .com 4 .com u datasheet
lvx family 16 datasheet table 3. code-data (top parameter) scsp memory map and partitioning flash die# die stack config. partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 1 code (top parameter) parameter partition (partition 0) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition 1 to 7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition 8 to 15) 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 2 data (bottom parameter) single partition 4x16 kword parameter blocks 127x64 kword main blocks (128 mb) 255x64 kword main blocks (256 mb) 64 128 130 7f0000-7fffff 256 258 ff0000-ffffff ... ... ... ... ... 64 67 400000-40ffff 131 800000-80ffff 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 19 100000-10ffff 64 10 070000-07ffff 18 0f0000-0fffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 16 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 16 0 000000-003fff 0 000000-003fff .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 17 table 4. code-data (bottom parameter) scsp memory map and partitioning flash die# die stack config. partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 2 data (top parameter) single partition 4x16 kword parameter blocks 127x64 kword main blocks (128 mb) 255x64 kword main blocks (256 mb) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 1 code (bottom parameter) main partitions (partitions 8 to 15) 64 128 130 7f0000-7fffff 256 258 ff0000-ffffff ... ... ... ... ... 64 67 400000-40ffff 131 800000-80ffff main partitions (partitions 1 to 7) 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 19 100000-10ffff parameter partition (partition 0) 64 10 070000-07ffff 18 0f0000-0fffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 16 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 16 0 000000-00ffff 0 000000-00ffff .com .com .com .com .com 4 .com u datasheet
lvx family 18 datasheet table 5. code-data (top - top paramete r) scsp memory map and partitioning flash die# die stack config. partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 1 code (top parameter) parameter partition (partition 0) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition 1 to 7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition 8 to 15) 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 2 data (top parameter) single partition 4x16 kword parameter blocks 127x64 kword main blocks (128 mb) 255x64 kword main blocks (256 mb) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 19 note: other stacked memory combinations and parameter configurations can be created based on the memory map and partitions highlighted from table 3 to table 7 . table 6. code-code-data (top parameter) scsp memory map and partitioning flash die# die stack config. partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 1 code (top parameter) parameter partition (partition 0) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition 1 to 7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition 8 to 15) 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 2 code (top parameter) parameter partition (partition 0) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff main partitions (partition 1 to 7) 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff main partitions (partition 8 to 15) 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 3 data (bottom parameter) single partition 4x16 kword parameter blocks 127x64 kword main blocks (128 mb) 255x64 kword main blocks (256 mb) 64 128 130 7f0000-7fffff 256 258 ff0000-ffffff ... ... ... ... ... 64 67 400000-40ffff 131 800000-80ffff 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 19 100000-10ffff 64 10 070000-07ffff 18 0f0000-0fffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 16 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 16 0 000000-003fff 0 000000-003fff .com .com .com .com .com 4 .com u datasheet
lvx family 20 datasheet note: other stacked memory combinations and parameter configurations can be created based on the memory map and partitions highlighted from table 3 to table 7 . table 7. code-code-data (bottom parameter) scsp memory map and partitioning flash die# die stack config. partitioning block size (kw) partition size (mbit) 128-mbit flash partition size (mbit) 256-mbit flash blk# address range blk# address range 3 data (top parameter) single partition 4x16 kword parameter blocks 127x64 kword main blocks (128 mb) 255x64 kword main blocks (256 mb) 16 8 130 7fc000-7fffff 16 258 ffc000-ffffff ... ... ... ... ... 16 127 7f0000-7f3fff 255 ff0000-ff3fff 64 126 7e0000-7effff 254 fe0000-feffff ... ... ... ... ... 64 120 780000-78ffff 240 f00000-ffffff 64 119 770000-77ffff 239 ef0000-efffff ... ... ... ... ... 64 64 400000-4fffff 128 800000-80ffff 64 63 3f0000-3fffff 127 f70000-f7ffff ... ... ... ... ... 64 0 000000-00ffff 0 000000-00ffff 2 code (bottom parameter) main partitions (partition 8 to 15) 64 130 7f0000-7fffff 258 ff0000-ffffff ... ... ... ... ... 64 67 400000-40ffff 131 800000-80ffff main partitions (partition 1 to 7) 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 19 100000-10ffff parameter partition (partition 0) 64 10 070000-07ffff 18 0f0000-0fffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 16 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 16 0 000000-003fff 0 000000-003fff 1 code (bottom parameter) main partitions (partition 8 to 15) 64 130 7f0000-7fffff 258 ff0000-ffffff ... ... ... ... ... 64 67 400000-40ffff 131 800000-80ffff main partitions (partition 1 to 7) 64 66 3f0000-3fffff 130 7f0000-7fffff ... ... ... ... ... 64 11 080000-08ffff 19 100000-10ffff parameter partition (partition 0) 64 10 070000-07ffff 18 0f0000-0fffff ... ... ... ... ... 64 4 010000-01ffff 4 010000-01ffff 16 3 00c000-00ffff 3 00c000-00ffff ... ... ... ... ... 16 0 000000-003fff 0 000000-003fff .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 21 3.0 package information lvx family with lpsdram device is available in the following standard scsp x 16d performance ballout packages: figure 4, ?lvx family with lpsdram device scsp x16d performance drawing 9x11x1.4 mm? on page 21 figure 5, ?lvx family with lpsdram device scsp x16d performance drawing 11x11x1.4 mm? on page 22 figure 4. lvx family with lpsdram device scsp x16d performance drawing 9x11x1.4 mm note: drawing not to scale. a y a2 a1 pin 1 corner d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m scsp top view - ball side down s1 s2 e dimensions symbol min nom max notes min nom max package height a 1.4 0.0551 ball height a1 0.200 0.0079 package body thickness a2 1.070 0.0421 ball (lead) width b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 10.90 11.00 11.10 0.4291 0.4331 0.4370 package body width e 8.90 9.00 9.10 0.3504 0.3543 0.3583 pitch e 0.800 0.0315 ball (lead) count n 103 103 seating plane coplanarity y 0.100 0.0039 corner to ball distance along e s1 1.200 1.300 1.400 0.0472 0.0512 0.0551 corner to ball distance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 .com .com .com .com .com 4 .com u datasheet
lvx family 22 datasheet figure 5. lvx family with lpsdram device scsp x16d performance drawing 11x11x1.4 mm millimeters inches dimensions symbol min nom max n otes min nom max package height a 1.4 0.0551 ball heig h t a 1 0.200 0.0079 package body thicknes s a2 1.070 0.0421 ball (lead) w idth b 0.325 0.375 0.425 0.0128 0.0148 0.0167 package body length d 10.90 11.00 11.10 0.4291 0.4331 0.4370 package body w idth e 10.90 11.00 11.10 0.4291 0.4331 0.4370 pitch e 0.800 0.0315 ball (lead) count n 103 103 seating plane coplanarity y 0.100 0.0039 corner to ball distance along e s1 2.200 2.300 2.400 0.0866 0.0906 0.0945 corner to ball distance along d s2 1.000 1.100 1.200 0.0394 0.0433 0.0472 note: drawing not to scale. pin 1 corner d e b a b c d e f g h j k 8 7 6 5 4 3 2 19 l m scsp top view - ball side down s1 s2 e a2 a1 a y .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 23 4.0 ballout and signal descriptions 4.1 signal ballout intel strataflash ? wireless memory system family is available in a x16d performance ballout, shown in figure 6, ?x16d (103 ball) performance signal ballout for lvx device family? the single package ballout is ideal for space-constrained board applications where density upgrades without pcb redesign is preferred. the user must adapt for density upgrade flexibility in the pcb design. figure 6. x16d (103 ball) performance signal ballout for lvx device family pin 1 123456789 adu a5 a7 a8a20a24a25a26dua ba3a4a6a18a19rfua23a27a17b c a2 vss vss vss r-vcc vss vss vss a16 c d a1 s-vcc r-vcc f-vcc adv# f-vcc r-vcc rfu a15 d e f-wp1# we# r2-cs# depop f4-ce# / a28 a22 a11 a14 e f f-wp2# r1-cs# d-cas# d-ras# s-cs1# a21 a10 a13 f g rfu f2-ce# f1-ce# d-ba0 d-cke f-rst# a9 a12 g h rfu s-cs2 f3-ce# d-ba1 rfu oe# d-dm1 / r-ub# d-dm0 / r-lb# h j f-vpp vccq vccq f-vcc r-clk f-vcc vccq vccq wait j k dq2 vss vss vss f-clk vss vss vss dq13 k l dq1 dq3 dq5 dq6 dq7 dq9 dq11 dq12 dq14 l m du dq0 rfu dq4 dq8 dq10 rfu dq15 du m 123456789 de-populated balls active balls legend: do not use top view - ball side down depop (rfus) reserved for future use .com .com .com .com .com 4 .com u datasheet
lvx family 24 datasheet 4.2 signal descriptions table 8 describes the active signals used on the lvx family with lpsdram device. table 8. signal descriptions (sheet 1 of 3) symbol type description notes a[max:1] input address: global device signals. share inputs for all memory die addresses during read and write operations. lpsdram address inputs also provide the op-code during a mode register set or special mode register set command. 256-mbit die: amax = a24 128-mbit die: amax = a23 64-mbit die: amax = a22 32-mbit die: amax = a21 8-mbit die: amax = a19 a[13:1] are the row and a[9:1] are the column addresses for 256-mbit lpsdram a[12:1] are the row and a[9:1] are the column addresses for 128-mbit lpsdram a11 defines the auto precharge. during a lpsdram precharge command, a11 is sampled to determine if all banks are to be precharged (a11 = high). 1,2 dq[15:0] input/ output data input/outputs: global device signals. inputs data and commands during write cycles, outputs data during read cycles. data signals float when the device or its output are deselected. data are internally latched during writes on the device. adv# input address valid: low-true input. (for stacked combinations without synchronous psram, adv# is a flash-specific input.) during synchronous flash read operations, addresses are latched on the rising edge of adv#, or on the next valid clk edge, whichever occurs first. in asynchronous flash read operation, addresses are latched on the rising edge adv#, or are continuously flow-through when adv# is kept asserted. f[4:1]-ce# input flash chip enable: low-true input. f[4:1]-ce# low selects the associated flash memory die. f[4:1]-ce# high deselects the associated flash die. when deasserted, the associated flash die is deselected, power is reduced to standby levels, data and wait outputs are placed in high-z state. f1-ce# is dedicated as flash code die #1. f[4:2]-ce# controls any subsequent flash die based on the user ordered scsp flash type combination. any unused f-ce# should be pulled high to f-vcc through a 1k-ohm resistor for future design flexibility. 3 f-clk, r-clk input device clock: synchronizes the selected memory die to the system bus clock in synchronous operations. performance ballout: f-clk is a flash signal. synchronizes the flash die to the system flash bus frequency in synchronous operations. r-clk is a lpsdram input signal. synchronizes the lpsdram die to the system?s memory bus clock. lpsdram is sampled on the positive edge of r-clk. oe# input output enable: global device signal. low-true input. oe# low enables the output drivers of the selected die. oe# high places the output drivers of the selected die in high-z. f-rst# input flash reset: flash specific signal. low-true input. f-rst# low resets internal operations and inhibits write operations. f-rst# high enables normal operation. exit from reset places the flash device in asynchronous read array mode. wait output device wait: selectable high-true or low-true output. (for stacked combinations without synchronous psram, wait is a flash specific input.) during synchronous-burst reads (array or non-array), wait-asserted indicates invalid read data. during asynchronous page reads and writes, wait is deasserted. wait is high-z whenever f-ce# or f-oe# / oe# is deasserted. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 25 we# input write enable: global device signal. low-true input. we# low selects the associated memory die for write operation. we# high deselect the associated memory die, data are placed in high-z state. with lpsdram operation, we# is latched on the positive clock edge in conjunction with the d-ras# and d-cas# signals. the we# input is used to select the bank activate or precharge command and read or write command. f-wp[2:1]# input write protect: low-true input. f-wp# controls the lock-down protection mechanism of the selected flash die. when low, f- wp# enables the lock-down mechanism where locked down blocks cannot be unlocked with software commands. when high, f-wp# disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. f-wp1# controls the code segment flash die #1, while f-wp2# controls subsequent code or data segment flash dies. d-cke input lpsdram clock enable: high-true input if d-cke goes low synchronously with clock, the internal clock is suspended from the next clock cycle. the state of the outputs and the burst address is halted. when all banks are in the idle state, d-cke is high, the lpdram enters into power- down and self refresh modes. d-cke is synchronous except after the device enters power-down and self refresh modes, where d-cke becomes asynchronous until exiting the same mode. the input buffers, including r-clk, are disabled during power-down and self refresh modes, providing low standby power. d-ba[1:0] input lpsdram bank select: d-ba0 and d-ba1 defines to which bank the bank activate, read, write, or bank precharge command is being applied. the bank address d-ba0 and d-ba1 is used latched in mode register set. d-ras# input lpsdram row address strobe: low-true input. the d-ras# signal defines the operation commands, with the d-cas# and we# signals. the d-ras# is latched at the rising edges of r-clk. when d-ras# and dx-cs# / rx- cs# are asserted and d-cas# is deasserted, either the bank activate command or the precharge command is selected by the we# signal. we# is deasserted, the bank activate command is selected and the bank designated by d-ba[1:0] is turned on to the active state. d-cas# input lpsdram column address strobe: low-true input. d-cas# signal defines the operation commands in conjunction with the d-ras# and we# signals and is latched at the rising edges of r-clk. d-ras# is deasserted and dx-cs# / rx-cs# is asserted, the column access is started by asserting d-cas#. read or write command then is selected by asserting we# low or high. r[2:1]-cs# input ram chip select: low-true input. x16d performance ballout: r[2:1]-cs# r[2:1]-cs# low selects the associated lpsdram memory die. all commands are masked when r[2:1]-cs# high. r[2:1]-cs# provides for external bank selection on systems with multiple banks. it is considered part of the command code. r1-cs# controls lpsdram die #1. r2-cs# controls lpsdram die #2. table 8. signal descriptions (sheet 2 of 3) symbol type description notes .com .com .com .com .com 4 .com u datasheet
lvx family 26 datasheet d-dm[1:0] input lpsdram data input/output mask: data input mask. d-dm[1:0] are byte selects. input data is masked when d-dm[1:0] are sampled high during a write cycle. d-dm1 masks dq[15-8], and d-dm0 masks dq[7-0]. the d-dm[1:0] latency for read is 2 clocks and for write is 0 clocks. 4 s-cs1# s-cs2 input sram chip selects: sram specific signal. low-true input. when both sram chip selects are asserted, sram internal control logic, input buffers, decoders, and sense amplifiers are active. when either or both sram chip selects are deasserted (s-cs1# = v ih and/or s-cs2 = v ih ), the sram is deselected and its power is reduced to standby levels. s-cs1# and s-cs2 are available on stacked combinations with sram die, and are rfu on stacked combinations without sram die. r-ub# r-lb# input sram upper/ lower byte enables: low - true inputs. during sram read and write cycles, r-ub# low enables the sram high-order byte on dq[15:8], and r-lb# low enables the sram low-order byte on dq[7:0]. r-ub# and r-lb# are available on stacked combinations with sram die, and are rfus on stacked combinations without sram die. 3,4 f-vpp power flash erase/ program voltage level: flash specific signal. valid f-vpp voltage on this ball allows block erase or program functions. flash memory array contents cannot be altered when f-v pp v pplk . block erase and program at invalid f- vpp voltage should not be attempted. f-vcc power flash core voltage level: flash specific signals. flash core source voltage. flash operations are inhibited when f-v cc v lko . operations at invalid f-vcc voltage should not be attempted. vccq power output voltage level: global device signals. device output-driver source voltage. this balls can be tied directly to the respective memory type x-vcc if operating within its x-vcc range. d-vcc, r-vcc power ram power supply: supplies power to the ram dies. performance ballout: d-vcc supplies power for lpsdram operation. x16d performance ballout: r-vcc supplies power for xram operation. s-vcc power sram power supply: supplies power to the sram die. s-vcc is available on stacked combinations with sram die, and is rfu on stacked combinations without sram die. vss power ground: connect to system ground. do not float any vss connection. du ? do not use: this ball must be left floating. this ball should not be connected to any power supplies, signals, or other balls. rfu ? reserved for future use: reserved by intel for future device functionality and enhancement. note: 1. all unused signals or rfus should be held either to a static vil or vih for future design flexibility and migrations. 2. a1 is the lowest order x16 address. 3. f4-ce# is a shared signal with a28 for the 103-active ball high performance dram package. 4. d-dm[1:0] are shared signals with r-ub# and r-lb# respectively. table 8. signal descriptions (sheet 3 of 3) symbol type description notes .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 27 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. notice: this document contains information available at the time of its release. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design . table 9. absolute maximum ratings parameter min max unit notes temperature under bias expanded ?25 +85 c storage temperature ?55 +125 c voltage on any signal (except f-v cc, f-v pp, r-v cc and v ccq ) ?0.2 +2.1 v 1 f-v cc voltage ?0.2 +2.50 v 1 v ccq , r-v cc voltage ?0.2 +2.45 v 1 f-v pp voltage ?0.2 +10.0 v 1,2,3 i sh output short circuit current ? 50 ma 4 notes: 1. voltage is referenced to v ss . 2. during power transitions, minimum dc voltage may undershoot to ?2.0 v for periods < 20 ns; maximum dc voltage may overshoot to v cc (operating max) + 2.0 v for periods < 20 ns. 3. during power transitions, minimum dc voltage may undershoot to ?1.0 v for periods < 20 ns; maximum dc voltage may overshoot to v ccq (operating max) + 1.0 v for periods < 20 ns. 4. during power transitions, minimum dc voltage may undershoot to ?2.0 v for periods < 20 ns; maximum dc voltage may overshoot to v pp2 (operating max) + 2.0 v for periods < 20 ns. 5. f-vpp can be v pp2 for 1000 cycles on main blocks, 2500 cycles on parameter blocks. 6. output shorted for no more than one second. no more than one output shorted at a time. .com .com .com .com .com 4 .com u datasheet
lvx family 28 datasheet 5.2 operating conditions warning: operation beyond the ?operating conditions? is not recommended and extended exposure beyond the ?operating conditions? may affect device reliability. table 10. extended temperature operation symbol parameter flash + xram units min max t c operating temperature ?25 +85 c f-v cc flash supply voltage 1.7 2.0 v v ccq r-v cc flash and lpsdram i/o voltage lpsdram supply voltage 1.7 1.9 v v ppl f-v pp voltage supply (logic level) 0.9 2 v v pph factory word programming f-v pp 8.5 9.5 v block erase cycles main and parameter blocks f-v pp = f-v cc 100,000 ? cycles main blocks f-v pp = v pph ? 1000 parameter blocks f-v pp = v pph ? 2500 note: operating voltage are for flash + flash only stacked device. refer to document numbers 253852 and 253853 for flash + ram stacked combinations. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 29 6.0 electrical specifications 6.1 dc voltage and current characteristics refer to the intel strataflash ? wireless memory (l18) datasheet (order number 251902) for flash dc characteristics. table 11, ?lpsdram dc characteristics? and table 12, ?lpsdram self refresh current? on page 30 show dc voltage and current characteristics for lpsdram. the dc current characteristics referenced in this document are for individual flash and ram die in the scsp device. the total device current is determined by sum of the active and inactive currents of each flash and ram die in the scsp device. notice: individual dc characteristics of all dies in a scsp device need to be considered accordingly, depending on the scsp device stacked combinations and operations. table 11. lpsdram dc characteristics (sheet 1 of 2) parameter description test conditions and density min typ max unit notes d-v cc / r-v cc voltage range 1.7 1.8 1.9 v i cc1 (one bank active) operating current at min cycle time burst length = 1 i io = 0ma t ck = min 128-mbit ? ? 60 ma 256-mbit ? ? 75 i cc2p precharge standby current: power-down mode (all banks idle) d-cke = l, dx-cs#/rx-cs# = h t ck = min 128-mbit ? ? 600 a 256-mbit ? ? 700 i cc2n precharge standby current: non-power- down mode (all banks idle) d-cke = h, dx-cs# = h t ck = min 128-mbit ? ? 15 ma 256-mbit ? ? 15 i cc3p active standby current in power-down mode (all banks active) d-cke = l, t ck = min 128-mbit ? ? 5 ma 256-mbit ? ? 5 i cc3n active standby current: non-power-down mode (all banks active) d-cke = h, t ck =min 128-mbit ? ? 20 ma 3 256-mbit ? ? 25 i cc4 (4 banks active) operating current page burst mode i io = 0ma t ck = min 128-mbit ? ? 70 ma 256-mbit ? ? 80 i cc5 auto refresh current t rc > t rcmin 128-mbit ? ? 130 ma 2 256-mbit ? ? 150 i cc6 self refresh current address & data toggling at min cycle time 128-mbit ? ? 500 a4 256-mbit ? ? 600 i cc7 deep power-down current address & data toggling at min cycle time 128-mbit ? ? 10 a 256-mbit ? ? 10 v oh output high voltage i oh = -100 ? ? v ccq ? 0.2 ??v .com .com .com .com .com 4 .com u datasheet
lvx family 30 datasheet v ol output low voltage i ol = 100 ? , v ccqmin ? ?0.1 ? 0.2 v v ih input high voltage ? ? v ccq ? 0.3 ? v ccq + 0.2 v v il input low voltage ? ? -0.2 ? 0.3 v i il input leakage current ?0.2 v < v in < v ccq +0.2 v ? ?1.5 ? +1.5 a1 notes: 1. input leakage currents include hi-z output leakage for bi-directional buffers with tri-state outputs. 2. input signals are toggled at max frequency to simulate scsp condition, where another device may be active. 3. no accesses in progress. 4. see table 12, ?lpsdram self refresh current? on page 30 . table 12. lpsdram self refresh current parameter description test condition set temperature # of banks unit all banks refreshed banks 0 & 1 refreshed bank 0 refreshed i cc6 (128-mbit) self refresh current (all banks refreshed) d-cke < 0.2v t ck = infinity 85 c max 500 400 300 a 70 c max 440 350 280 45 c max 390 290 260 15 c max 350 240 240 i cc6 (256-mbit) self refresh current (all banks refreshed) d-cke < 0.2v t ck = infinity 85 c max 600 450 315 a 70 c max 525 375 295 45 c max 450 300 270 15 c max 375 250 250 note: other than i cc6 for all banks at 85 c, the self refresh currents are verified during device characterization and not 100% tested. table 11. lpsdram dc characteristics (sheet 2 of 2) .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 31 7.0 ac characteristics 7.1 device ac test conditions note: ac test inputs are driven at v ccq for logic "1" and 0.0 v for logic "0." input/output timing begins/ends at v ccq /2. input rise and fall times (10% to 90%) < 5 ns. worst case speed occurs at f-v cc = f-v cc min . notes: 1. test configuration component value for worst case speed conditions. 2. c l includes jig capacitance. 7.2 capacitance 7.3 flash ac read operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for flash read and write ac characteristics. figure 7. ac input/output reference waveform io_ref.wmf input v ccq /2 v ccq /2 output v ccq 0v test points figure 8. transient equivalent testing load circuit 1,2 r-vcc/2 notice: refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for flash capacitance details. table 13. lpsdram capacitance symbol parameter max unit condition c in input capacitance 5 pf v in = 0 v c out output capacitance 7 pf v out = 0 v note: sampled, not 100% tested. t c = +25 c, f = 1 mhz. .com .com .com .com .com 4 .com u datasheet
lvx family 32 datasheet 7.4 flash ac write operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for flash read and write ac characteristics. 7.5 lpsdram ac characteristics table 14, ?lpsdram ac characteristics?read-only operations? on page 32 and table 15, ?lpsdram ac characteristics?write operations? on page 33 list the ac characteristics for the lpsdram die. table 14. lpsdram ac characteristics?read-only operations (sheet 1 of 2) symbol parameter min max unit t rc clock cycle time cl = 3 (125 mhz) 9.5 (105) ? ns cl = 2 (100 mhz) 15 (66) ? cl = 1 (50 mhz) ? ? t ckh clock high level pulse width 3 ? ns t ckl clock low level pulse width 3 ? ns t t transition time 0.5 1.0 ns t ckeh d-cke hold time 1?ns t ckes d-cke setup time 2?ns t ah address hold time 1?ns t as address setup time 2?ns t ih data input hold time 1 ? ns t is data input setup time 2 ? ns t cmh dx-cs#,d-ras#,d-cas#,we#,d-dm hold time 1 ? ns t cms dx-cs#,d-ras#,d-cas#,we#,d-dm setup time 2 ? ns t ac clock to valid output delay (positive edge of clock) cl = 3 ? 7 ns cl = 2 ? 9 cl = 1 ? ? t oh data out hold time 2.5 ? ns t lz clock to output in low-z 1 ? ns t hz clock to output in high-z cl = 3 ? 7 ns cl = 2 ? 9 cl = 1 ? ? t ras row active time (active to precharge cmd) 60 100k ns t rc row cycle time (active to active cmd on same bank) 90 ? ns t rcd row to column delay (active to read/write) 30 ? ns t rp row precharge time 30 ? ns t ref refresh period (4096 rows) ? 64 ms .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 33 t rfc auto refresh period 110 ? ns t srex self refresh exit time (self refresh to active) 120 ? ns notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required by clock cycle time. 2. lpsdram ac specs are guaranteed only when normal output driver strength is used. see table 25 . table 15. lpsdram ac characteristics?write operations symbol parameter min max unit t wr write recovery time 20 ? ns t rrd active bank a to active bank b command 20 ? ns t dal last data input to active delay ? t wr + t rp t cdl last data input to new read/write command ? 1 t ck t bdl last data input to burst terminate command ? 1 t ck t ccd read/write command to read/write command ? 1 t ck t dqw d-dm write mask latency ? 0 t ck t dqz d-dm data out mask latency ? 2 t ck t mrd load mode register command to active/refresh command ? 2 t ck t wr write recovery time t wr / t ck < 1 ? 1 t ck 1 < t wr / t ck < 2 ? 2 t phz data out to high z from precharge command cl = 3 ? 3 t ck cl = 2 ? 2 cl = 1 ? ? t ini initialization delay 200 ? s notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required by clock cycle time. 2. lpsdram ac specs are guaranteed only when normal output driver strength is used. see table 25 . table 14. lpsdram ac characteristics?read-only operations (sheet 2 of 2) symbol parameter min max unit .com .com .com .com .com 4 .com u datasheet
lvx family 34 datasheet 8.0 power and reset specifications refer to the latest revision of the intel strataflash ? wireless memory system (lv18/lv30 scsp; 1024-mbit lv family datasheet (order number 253854) for details not included in this document. 9.0 operations overview 9.1 bus operations bus operations for this l18 scsp lvx family (x16) device involve the control of flash and lpsdram inputs. the bus operations and commands are shown in the following tables: table 16, ?flash and lpsdram bus operations? on page 35 table 17, ?lpsdram functional mode description: current state bank n, command to bank n? on page 38 table 18, ?lpsdram functional mode: current state bank n, command to bank m? on page 39 fully synchronous operations are performed by the lpsdram to latch the commands at the positive edges of r-clk. refer to the intel strataflash ? wireless memory (l18) datasheet (order number 251902) for complete descriptions of flash modes and commands, command bus-cycle definitions and flowcharts that illustrate operational routines. table 16, ?flash and lpsdram bus operations? summarizes the bus operations and voltage levels that must be applied to individual flash die in each mode. refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for complete descriptions of flash modes and commands, for command bus-cycle definitions, and flowcharts that illustrate operational routines. each flash die within the lvx system shares basic asynchronous read and write operations unless otherwise specified. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 35 table 16. flash and lpsdram bus operations (sheet 1 of 3) device mode f-rst# fx-ce# oe# adv# f-vpp wait we# d-cke n-1 d-cke n dx-cs# d-ras# d-cas# d-dm[1:0] d-ba[1:0] a11 address data notes flash die (code) sync array read hlll x active h lpsdram outputs must be in high-z flash d out 1,4,6, 16 async read hllx x deassertedh flash d out 1,4,5, 6,16 write h l h l v pp1/ v pp2 high-z l flash d in 2,3,5, 6 output disable h l h x x high-z h any lpsdram mode allowed flash high-z 6 standby h h x x x high-z x flash high-z 6 reset l x x x x high-z x flash high-z 6 flash die (data) sync array read hlll x deassertedh lpsdram outputs must be in high-z flash d out 1,4,6, 16 async read hllx x deassertedh flash d out 1,4,5, 6,16 write h l h l v pp1/ v pp2 deasserted l flash d in 2,3,5, 6 output disable h l h x x high-z h any lpsdram mode allowed flash high-z 6 standby h h x x x high-z x flash high-z 6 reset l x x x x high-z x flash high-z 6 .com .com .com .com .com 4 .com u datasheet
lvx family 36 datasheet lpsdram die (#1 or #2) active flash outputs must be in high-z hhxllh x v row address ram d out 6,7 read hhxlhll/hv l col addr ram d out 6,7,8, 10 with auto precharge h write lhxlhll/hv l x ram d in 6,9,10 with auto precharge h burst stop l h h l h h x x x x ram high-z 6 precharge one bank lhxllh x vl x ram high-z 6 all banks xh auto refresh flash must be in high-z hhhlll x x x x ram high-z 6,13 self refresh entry hhl lll x x x x ram high-z 6,13 self refresh exit h lh lhh xxx x ram high-z 6 any flash mode allowed x h x x table 16. flash and lpsdram bus operations (sheet 2 of 3) device mode f-rst# fx-ce# oe# adv# f-vpp wait we# d-cke n-1 d-cke n dx-cs# d-ras# d-cas# d-dm[1:0] d-ba[1:0] a11 address data notes .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 37 lpsdram die (#1 or #2) load mode register flash outputs must be in high-z l h x l l l x operand code ram high-z 6,11,1 2 input/ output enable xh x l x ram high-z 6,10 input inhibit/ output high-z any flash mode allowed xh x h x ram high-z 6,10 clock suspend entry x hl hxx xxx x ram high-z 6,14 flash outputs must be in high-z vlvv clock suspend exit xlhxxx x x x x ram high-z 6 power- down entry any flash mode allowed x hl hxx xxx x ram high-z 6,15 flash outputs must be in high-z h l h h power- down exit any flash mode allowed x lh hxx xxx x ram high-z 6 flash outputs must be in high-z hlhh deep power- down entry lhllhh x x x x ram high-z 6 deep power- down exit xlhxxx x x x x ram high-z 6 device deselect any flash mode allowed x h x h x x x x x x ram high-z 6 no operation flash outputs must be in high-z h h x l h h x x x x ram high-z 6 notes: 1. wait is only valid during synchronous flash reads. refer to the discrete datasheet for detailed wait functionality. 2. oe# and we# (flash and sram) should never be asserted simultaneously. 3. x can be v il or v ih for inputs, v pp1 , v pp2 or v pplk for f-v pp . 4. flash cfi query and status register accesses use dq[7:0] only, all other reads use dq[15:0]. 5. refer to l18 datasheets for valid d in during flash writes. 6. all states and sequences not shown are illegal or reserved. 7. a[13:1] provide row address for 256-mbit lpsdram. a[12:1] provide row address for 128-mbit lpsdram. a[9:1] provide column address for 128-mbit or 256-mbit lpsdram. 8. select bank and column address, and start read. a11 high enables auto precharge. 9. select bank and column address, and start write. a11 high enables auto precharge. 10.activate or deactivate the data during writes with zero-clock delay and during reads with two-clock delay. d-dm0 corresponds to dq[7:0], d-dm1 corresponds to dq[15:8]. 11. a[11:1] define the operand code to the register 12.extended mode register is programmed by setting d-ba1=h and d-ba0=l. for mode register programming, set d-ba1=d- ba0=l 13.all banks must be precharged before issuing an auto-refresh command. 14.clock suspend mode occurs when column access or burst is in progress 15.power-down occurs when no accesses are in progress. 16.data segment flash only operates in asynchronous mode, f-clk is ignored and wait is deasserted. table 16. flash and lpsdram bus operations (sheet 3 of 3) device mode f-rst# fx-ce# oe# adv# f-vpp wait we# d-cke n-1 d-cke n dx-cs# d-ras# d-cas# d-dm[1:0] d-ba[1:0] a11 address data notes .com .com .com .com .com 4 .com u datasheet
lvx family 38 datasheet table 17. lpsdram functional mode description: current state bank n , command to bank n current state dx-cs# d-ras# d-cas# we# command action notes any hxxxno operation continue previous operation l hhhno operation continue previous operation idle l l h h active select and activate row lllhauto refresh auto refresh llllload mode register mode register set llhlprecharge nop row active l h l h read select column & start read burst l h l l write select column & start write burst l l h l precharge deactivate row in bank (or banks) 3 read (without auto precharge) l h l h read truncate read & start new read burst 5 l h l l write truncate read & start new write burst 5 l l h l precharge truncate read, start precharge l h h l burst terminate burst terminate write (without auto precharge) l h l h read truncate write & start new read burst 5 l h l l write truncate write & start new write burst 5 l l h l precharge truncate write, start precharge l h h l burst terminate burst terminate notes: 1. the table applies when both d-cke n-1 and d-cke n are high. 2. all states and sequences not shown are illegal or reserved. 3. this command may or may not be bank specific. if all banks are being precharged, they must be in a valid state for precharging. 4. a command other than no operation (nop), should not be issued to the same bank while a read or write burst with auto precharge is enabled. 5. the new read or write command could be auto precharge enabled or auto precharge disabled. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 39 table 18. lpsdram functional mode: current state bank n , command to bank m current state dx-cs# d-ras# d-cas# we# command action notes any h x x x no operation continue previous operation l h h h no operation continue previous operation idle x x x x any any command allowed to bank m row activating, active, or precharging l l h h active activate row l h l h read start read burst lhllwrite start write burst l l h l precharge precharge read with auto precharge disabled l l h h active activate row l h l h read start read burst lhllwrite start write burst l l h l precharge precharge write with auto precharge disabled l l h h active activate row l h l h read start read burst lhllwrite start write burst l l h l precharge precharge read with auto precharge l l h h active activate row l h l h read start read burst lhllwrite start write burst l l h l precharge precharge write with auto precharge l l h h active activate row l h l h read start read burst lhllwrite start write burst l l h l precharge precharge notes: 1. the table applies when both d-cke n-1 and d-cke n are high. 2. all states and sequences not shown are illegal or reserved. .com .com .com .com .com 4 .com u datasheet
lvx family 40 datasheet 10.0 flash read operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for information regarding flash read modes and operations. 11.0 flash program operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for information regarding flash program operations. 12.0 flash erase operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for information regarding flash erase operations. 13.0 flash suspend and resume operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for information regarding flash security modes and operations. 14.0 flash block locking a nd unlocking operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for information regarding flash read configura tion register (rcr) functions and programming. 15.0 flash protection register operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for information regarding flash power considerations and consumption. 16.0 flash configuration operations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for information regarding flash read configura tion register (rcr) functions and programming. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 41 17.0 flash dual operation considerations refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for information regarding flash read configura tion register (rcr) functions and programming. 18.0 lpsdram operations 18.1 lpsdram power-up sequence and initialization the lpsdram must be powered up and initialized in a predefined manner. once power is applied to d-vcc and vccq simultaneously, and the clock is stable, the lpsdram requires a t ini delay prior to issuing any command other than the nop command. the nop command should be applied at least once during the t ini delay. after the t ini delay, a precharge command should be applied to precharge all banks. this must be followed by two back to back auto refresh cycles. after the auto refresh cycles are complete, the mode registers must be programmed. the mode register will power up in an unknown state. the mode register and the extended mode register should be loaded prior to issuing any operational commands. 18.2 lpsdram mode register the mode register is used to define specific modes of operation of the lpsdram. this definition includes the selection of a burst length, burst type, a cas latency, and a write burst mode. the mode register settings are illustrated in the table below. the mode register is programmed by the load mode register command and will retain the information until it is reprogrammed, the device loses power, or the device goes in deep power-down mode. the register should be loaded when all banks are idle, and subsequent operation should only be initiated after t mrd . addresses a[12:11, 9:8] must be set to 0 for all mode register programming. d-ba[1:0] should be set to (0,0) to differentiate from extended mode register programming. table 19. lpsdram setting for burst length burst length a3 a2 a1 a4 = 0 a4 = 1 1 1 000 2 2 001 4 4 010 8 8 011 full page reserved 1 1 1 notes: 1. states not mentioned are undefined. 2. the sequential burst will wrap on reaching the last column of the burst length. .com .com .com .com .com 4 .com u datasheet
lvx family 42 datasheet 18.3 extended mode register the extended mode register (emr) controls two power saving functions: temperature-compensated self refresh (tcsr) partial array self refresh (pasr) both these features can only be used when the device is under self refresh. in addition the configurable output driver strength can be programmed through the emr. the emr is programmed by the load mode register command and will retain the information until it is reprogrammed, the device loses power, or the device goes into deep power-down mode. the register should be loaded when all banks are idle, and subsequent operation should only be initiated after t mrd . to program the emr, bank addresses d-ba1 = 1, and d-ba0 = 0 should be used. addresses a[12:6] should be set to '0'. table 20. lpsdram setting for burst type a4 burst type 0 sequential 1 interleaved table 21. lpsdram setting for cas latency a7 a6 a5 cas latency 001 1 010 2 011 3 note: states not mentioned are undefined. table 22. lpsdram setting for write burst mode a10 write burst mode 0 programmed burst 1 single word burst table 23. lpsdram setting for partial array refresh a3 a2 a1 self-refresh coverage 000 four banks 0 0 1 two banks (bank 0 & bank 1) 0 1 0 one bank (bank 0) .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 43 18.4 lpsdram commands and operations 18.4.1 lpsdram no operation / device deselect the lpsdram device includes a device deselect (nop) command and a no operation (nop) command. 18.4.1.1 device deselect (nop) the device deselect (nop) command deselects the lpsdram by preventing new commands from being executed. operations already in progress are not affected. 18.4.1.2 no operation (nop) the no operation (nop) command is used on a lpsdram device that is selected (d-cs# / r-ds# is low). operations already in progress are not affected. 18.4.2 lpsdram active the active command is used to activate a row in particular bank for a subsequent read or write access. the value of the bank d-ba[1:0] and the row address needs to be provided. the row remains active until a precharge command is issued to the bank. a precharge command must be issued before opening a different row in the same bank. more than one bank can be active at any time. a read or write command could be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which the read/write can be entered. a subsequent active command to another row in table 24. lpsdram setting for temperature-compensated self refresh a5 a4 maximum ambient temperature 1 1 85 c 0 0 70 c 0 1 45 c 1 0 15 c table 25. configurable output driver strength a7 a6 strength output load (pf) 0 0 normal 30 01 half tbd 1 0 reserved na 1 1 reserved na note: lpsdram ac specs are guaranteed only when normal output driver strength is used. .com .com .com .com .com 4 .com u datasheet
lvx family 44 datasheet the same bank can be issued only after the previous row has been closed. the minimum time interval between two successive active commands on the same bank is defined by t rc . the minimum time interval between two successive active commands on the different banks is defined by t rrd . this is illustrated in figure 11, ?active command and read access command issued to 2 different banks? on page 47 . 18.4.3 lpsdram read the read command is used to initiate a burst read to an active row. the value of d-ba[1:0] selects the bank and address inputs select the starting column location. the value of a11 determines whether or not auto precharge is used. output data appears on the data bus, subject to the logic level on the d-dm[1:0] inputs two clocks earlier. d-dm[1:0] latency for the read command is 2 clock cycles. the burst length is set in the mode register. the starting column and bank address is provided along with the auto precharge option. during read bursts, the starting valid data-out corresponding to the starting column address will be available after cas latency cycles after the read command. each subsequent data-out will be valid by the next positive edge of the clock. this is shown in figure 12, ?example of cas latency 2? on page 47 with a cas latency of 2. data from a read burst may be truncated by a subsequent read command. the first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. the new read command can be issued as early as cl-1 cycles before the last desired element. this is shown in figure 13, ?consecutive read bursts with cl = 2? on page 48 . figure 14, ?random read access with cl = 2? on page 48 shows random access reads. these can be issued to the same or different banks. a read burst can be terminated by a subsequent write command, and data from a fixed length read burst can be followed by a write command. the write command can be initiated on the clock edge immediately following the last data element from the read burst, provided i/o contention can be avoided. d-dm[1:0] can be used to control i/o contention as shown in figure 15, ?read to write command? on page 48 . d-dm[1:0] latency is 2 clocks for output buffers masking, so the d- dm[1:0] signal must be set high at least 2 clocks prior to the write command. d-dm[1:0] latency for write is zero clocks, so d-dm[1:0] must be set low before write command to ensure data written is not masked. a read burst may be followed by or truncated with a precharge command, which could be issued cl-1 cycles before the last desired element. this is shown in figure 16, ?read command followed by precharge? on page 49 . following a precharge command, another command to the same bank cannot be issued until t rp is met. similarly a burst terminate command can be used to stop a burst as shown in figure 17, ?read followed by burst terminate? on page 49 . 18.4.4 lpsdram write the write command initiates a burst write access to an active row. the value of d-ba[1:0] selects the bank. address inputs select the starting column location. the value of a11 determines whether or not auto precharge is used. input data appearing on the data bus, is written to the memory array subject to the d-dm[1:0] input logic level appearing coincident with the data. d-dm[1:0] latency for write command is 0 clock cycles. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 45 the burst length is set in the mode register. the starting column and bank address is provided along with the auto precharge option. the first valid data-in is registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. figure 18, ?random write to 4 word bursts? on page 49 shows 2 consecutive 4 word write bursts. a write burst may be followed by or truncated with a precharge command to the same bank. the precharge should be issued t wr after the clock edge after the last desired input data is entered. in addition, when truncating a write burst, the d-dm[1:0] signal must be used to mask input data for the clock edge coincident with the precharge command. this is shown in the following: figure 19, ?write to precharge command where write recovery takes 1 clock cycle? on page 50 figure 20, ?write to precharge command where write recovery takes 2 clock cycles? on page 50 where t wr corresponds to either 1 or 2 clock cycles, respectively. following the precharge command, a subsequent command cannot be issued to the same bank until t rp is met. write burst can be truncated with a burst terminate command. while truncating, the input data being applied coincident to the burst terminate will be ignored. data for any writes may be truncated by a subsequent read command as shown in figure 21, ?write command followed by read command? on page 50 . once the read command is registered, the data inputs will be ignored. 18.4.5 lpsdram power-down power-down occurs if d-cke is set low coincident with device deselect or nop command and when no accesses are in progress. if power-down occurs when all banks are idle, it is precharge power-down. if power-down occurs when one or more banks are active, it is referred to as active power- down. the device cannot stay in this mode fo r longer than the refresh period (64ms) without losing data. the power-down state is exited by setting d-cke high while issuing a device deselect or nop command. this is shown in figure 22, ?precharge power-down mode? on page 51 . 18.4.6 lpsdram deep power-down the deep power-down (dpd) mode enables very low standby currents. all internal voltage generators inside the lpsdram are stopped and all memory data are lost in this mode. to enter the dpd mode, all banks must be precharged, prior to the dpd command. to exit this mode, the d- cke is taken high after the clock is stable. 18.4.7 lpsdram clock suspend this mode occurs when a column access or burst is in progress, and d-cke is set low. the internal clock gets suspended freezing the lpsdram logi c. any command or data present on the input pins at the time of suspended internal clock is ignored. the output data on the pins stays frozen. this mode is exited by setting d-cke high, which results in the operation being resumed. figure .com .com .com .com .com 4 .com u datasheet
lvx family 46 datasheet 23, ?clock suspend during write burst? on page 51 shows a clock suspend during a write burst and figure 24, ?clock suspend during read burst (cl = 2)? on page 52 shows a clock suspend during a read burst. 18.4.8 lpsdram precharge the precharge is used to deactivate an active row in a particular bank or active row in all banks. the banks will be available for row access after a specified time (t rp ) after the precharge command is issued. if one bank is to precharged, the particular bank address needs to be addressed. if all banks are to be precharged, a11 should be set high along with the precharge command. 18.4.9 lpsdram auto precharge auto precharge is accomplished when a11 is high, to enable auto precharge in conjunction with a specific read or write command. this precharges the row after the read or write burst is complete. auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. another command to the same bank must not be issued until the precharge time (t rp ) is completed. auto precharge does not apply in full-page burst mode. auto precharge is non- persistent. 18.4.10 lpsdram concurrent auto precharge if an access command with auto precharge enabled is being executed, it can be interrupted by another access command. figure 25, ?read with auto precharge to bank n interrupted by read to bank m? on page 52 shows a read with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the read to bank m will interrupt the read to bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered. figure 26, ?read with auto precharge to bank n interrupted by write to bank m? on page 53 shows a read with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the precharge to bank n will begin when the write to bank m is registered. d-dm[1:0] should be set high 2 clock before the write command to prevent bus contention. figure 27, ?write with auto precharge to bank n interrupted by read to bank m? on page 53 shows a write with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the new command initiates bank n write recovery (t wr ) followed by precharge. the last valid data-in to bank n is 1 clock prior to the read to bank m. figure 28, ?write with auto precharge to bank n interrupted by write to bank m? on page 53 shows a write with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the new command initiates bank n write recovery (t wr ) followed by precharge. the last valid data-in to bank n is 1 clock prior to the write to bank m. figure 9. auto refresh cycles with d-cke high t0 t1 t2 tn tm t rp t rfc t rfc command precharge nop auto refresh auto refresh active r-clk .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 47 figure 10. self refresh entry and exit mode figure 11. active command and read access command issued to 2 different banks figure 12. example of cas latency 2 t0 t1 t2 tn tm t rp command precharge nop auto refresh nop auto refresh t srex > t ras r-clk d-cke t0 t1 t2 t3 t4 t5 t6 t7 command active nop read-ap nop active nop read-ap nop t rcd, bank 0 address bk 0/row bk 0/col a bk 1/row bk1/ col b t rrd data i/o dout - a dout-a+1 dout-a+2 t ras, bank 0 r-clk r-clk t0 t1 t2 t3 command read nop nop nop t oh dout t hz cl=2 t as t ah t lz t ac .com .com .com .com .com 4 .com u datasheet
lvx family 48 datasheet note: a new command should be issued cl-1 clock cycles before the last desired data. the new command can be used to truncate the previous read burst. note: data masking used to prevent i/o contention. figure 13. consecutive read bursts with cl = 2 r-clk t0 t1 t2 t3 t4 t5 t6 command read nop nop nop read nop nop address bk n /col a bk any/col b data i/o dout - a dout-a+1 dout-a+2 dout - a+3 dout - b cl - 1 figure 14. random read access with cl = 2 figure 15. read to write command r-clk t0 t1 t2 t3 t4 t5 t6 command read read read read nop nop nop address bk any/col a bk any/col b bk any/col c bk any/col d data i/o dout - a dout - b dout - c dout - d r-clk t0 t1 t2 t3 t4 command read nop nop nop write address bk n /col a bk any/col b data i/o dout - a dout-a+1 din - b d-dm .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 49 note: command issued cl-1 clocks before last desired data-out element. note: the commands can be to any active bank. figure 16. read command followed by precharge figure 17. read followed by burst terminate figure 18. random write to 4 word bursts r-clk t0 t1 t2 t3 t4 t5 t6 t7 command read nop nop nop precharge nop nop active address bk n /col a bk n/all bk/row data i/o dout - a dout-a+1 dout-a+2 dout - a+3 cl - 1 cl=2 t0 t1 t2 t3 t4 t5 t6 command read nop nop nop brst term nop nop address bk n /col a data i/o dout - a dout-a+1 dout-a+2 dout - a+3 cl - 1 cl=2 r-clk t0 t1 t2 t3 t4 t5 t6 clk commandwritenop nop nop writenop nop address bk n /col a bk any/col b data i/o din - a din-a+1 din-a+2 din - a+3 din - b din - b+1 din - b+2 r-clk .com .com .com .com .com 4 .com u datasheet
lvx family 50 datasheet note: the read and write commands can be done to any bank (cl = 2). figure 19. write to precharge command where write recovery takes 1 clock cycle figure 20. write to precharge command where write recovery takes 2 clock cycles figure 21. write command followed by read command t0 t1 t2 t3 t4 t5 t6 clk dqm command write nop precharge nop nop active nop t rp address bk n /col a bk a/all bk any/col b t wr data i/o din - a din-a+1 r-clk d-dm r-clk d-dm t0 t1 t2 t3 t4 t5 t6 command write nop nop precharge nop nop active t rp address bk n /col a bk a/all bk any/col b t wr data i/o din - a din-a+1 t0 t1 t2 t3 t4 t5 clk command write nop read nop nop nop address bk n /col a bk a ny /col b data i/o din - a din - a+1 dout - b dout - b+1 cl=2 r-clk .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 51 note: all banks are idle with d-cke low. note: input data is ignored when internal clock is suspended. figure 22. precharge power-down mode figure 23. clock suspend during write burst t0 t1 t2 tn tn+1 clk cke two clk cycles command precharge nop nop nop active all banks a10 row single bank ba0, ba1 bank row data i/o high-z d-cke a11 d-ba[1:0] r-clk t0 t1 t2 t3 t4 t5 clk cke internal clock command nop write nop nop address bk n /col a bk any/col b data i/o din - a din - a+1 din - a+2 d-cke r-clk .com .com .com .com .com 4 .com u datasheet
lvx family 52 datasheet note: output data gets frozen while internal clock is suspended. figure 24. clock suspend during read burst (cl = 2) figure 25. read with auto precharge to bank n interrupted by read to bank m t0 t1 t2 t3 t4 t5 t6 clk cke internal clock command read nop nop nop nop nop address bk n /col a data i/o dout - a dout-a+1 dout - a+2 dout - a+3 d-cke r-clk t0 t1 t2 t3 t4 t5 t6 bank n bank m command nop read-ap nop read-ap nop nop nop t rp , bank n bank n page active read burst interrupt burst, precharge idle bank m page active read burst address bk n /col a bk m/col b cl=2 data i/o dout - a dout - a+1 dout - b dout - b+1 r-clk .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 53 figure 26. read with auto precharge to bank n interrupted by write to bank m figure 27. write with auto precharge to bank n interrupted by read to bank m figure 28. write with auto precharge to bank n interrupted by write to bank m t0 t1 t2 t3 t4 t5 t6 bank n bank m command nop read-ap nop nop write-ap nop nop t rp , bank n bank n page active read burst interrupt burst, precharge bank m page active write burst address bk n /col a bk m/col b cl=2 data i/o dout - a din - b din - b+1 din - b+2 r-clk d-dm t0 t1 t2 t3 t4 t5 t6 clk bank n bank m command write-ap nop read-ap nop nop nop nop t wr , bank n t rp , bank n bank n active write burst interrupt burst, write recovery precharge bank m page active read burst (4 word) precharge address bk n /col a bk m/col b data i/o din -a din -a+1 dout - b dout - b+1 dout - b+2 r-clk t0 t1 t2 t3 t4 t5 t6 clk bank n bank m command write-ap nop write-ap nop nop nop nop t wr , bank n t rp , bank n bank n active write burst (4 word) interrupt burst, write recovery precharge t wr , bank m bank m page active write burst (4 word) wrtie recovery address bk n /col a bk m/col b data i/o din -a din -a+1 din - b din - b+1 din - b+2 din - b+3 r-clk .com .com .com .com .com 4 .com u datasheet
lvx family 54 datasheet 18.4.11 lpsdram burst terminate this command is used to truncate bursts. the most recent command prior to the burst terminate command will be truncated. 18.4.12 lpsdram auto refresh this command is used during normal operation of the lpsdram. this command is non- persistent. all banks must be idle before issuing auto refresh command. this command can be issued after a minimum of t rp after the precharge command. the address bits are "do not care" during the auto refresh command. as an example, the 128-mbit lpsdram requires 4096 auto refresh cycles (4096 rows/bank) every 64 ms (t ref ). providing a distributed auto refresh command every 15.625 s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 4096 auto refresh command cycles can be issued in a burst at a minimum cycle rate (t rfc ), once every 64 ms. figure 9, ?auto refresh cycles with d-cke high? on page 46 shows auto refresh cycles. 18.4.13 lpsdram self refresh this state retains data in the lpsdram, even as the rest of the system is powered down. the self refresh command is initiated like the auto refresh command, except the d-cke is disabled (low). all banks must be idle before this command is issued. once the self refresh command is registered, all inputs become "do not care" except d-cke, which must remain low. the procedure for exiting self refresh mode requires a series of commands. the first clock must be stable before d-cke going high. nop commands should be issued (minimum of 2 clocks) to meet the refresh exit time (t srex ) limitation. figure 10, ?self refresh entry and exit mode? on page 47 shows self refresh entry and exit mode. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 55 appendix a write state machine refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for the write state machine (wsm) details. appendix b common flash interface refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for the common flash interface (cfi) details. appendix c flash flowcharts refer to the intel strataflash ? wireless memory system datasheet (order number 253854) for the flash flowchart details. .com .com .com .com .com 4 .com u datasheet
lvx family 56 datasheet appendix d additional information : document number datasheets 253854 intel strataflash ? wireless memory system (lv18/lv30 scsp) datasheet application notes 253856 concurren t program and erase using the intel strataflash ? wireless memory system (l18/l30 scsp) 292221 ap-663 using the intel strataflash ? memory write buffer ? 292286 ap-738 reduce manufacturing costs with intel ? flash memory enhanced factory programming 251237 ap-759 intel ? flash memory programming algorithm optimizations 297769 ap-678 improving programming throughput of automated flash memories 292186 ap-630 designing for on-board programming using ieee1149.1 (jtag) access port 292185 ap-629 simplifying manufacturing by using automatic test equipment for on-board programming software manuals 297833 intel ? flash data integrator (fdi) user?s guide 298136 intel ? persistent storage manager (psm) 298132 intel ? virtual small block file manager (vfm) scsp user guide 298161 intel ? flash memory chip scale package user?s guide notes: 1. call the intel literature center at (800) 548-4725 to request intel documentation. international customers must contact their local intel or distribution sales office. 2. for the most current information on intel ? flash memory products, software and tools, visit http:// developer.intel.com/design/flash. .com .com .com .com .com 4 .com u datasheet
lvx family datasheet 57 appendix e ordering information the following figures and tables provide ordering information for the lvx family with lpsdram device flash + ram combinations: table 26, ?lvx family with lpsdram: available product ordering information? figure 29, ?lvx family with lpsdram: ordering information decoder? on page 58 table 27, ?38f and 48f product densities? on page 58 . table 26. lvx family with lpsdram: a vailable product ordering information i/o voltage (v) flash density (mbit) and family ram density (mbit) and ram type package part number notes size (mm) ballout name ball type 1.8 256 l18 + 256 l18 + 256 v18 + 256 v18 ?11x11x1.4 x16d (103 ball) scsp leaded rd48f4444lvybb0 rd48f4444lvytb0 256 l18 + 256 v18 128 sdram 9x11x1.4 x16d (103 ball) scsp leaded RD38F4460LVYbb0 RD38F4460LVYtb0 RD38F4460LVYgb0 1 256 l18 + 256 l18 + 256 v18 128 sdram 9x11x1.4 x16d (103 ball) scsp leaded rd58f0012lvybb0 rd58f0012lvytb0 2 256 l18 + 256 v18 + 256 v18 128 sdram 9x11x1.4 x16d (103 ball) scsp leaded rd58f0016lvybb0 rd58f0016lvytb0 2 notes: 1. for RD38F4460LVYgb0, the ?g? designates a f-ce# parameter configuration where f1-ce# = top parameter and f2-ce# = top parameter. 2. the 58fxxxx nomenclature indicates that more than three flash + ram dies are used in the stacked device. .com .com .com .com .com 4 .com u datasheet
lvx family 58 datasheet figure 29. lvx family with lpsdram: ordering information decoder table 27. 38f and 48f product densities code flash die density ram die density 0 no die no die 1 32-mbit 4-mbit 2 64-mbit 8-mbit 3 128-mbit 16-mbit 4 256-mbit 32-mbit 5 512-mbit 64-mbit 6 1-gbit 128-mbit 7 2-gbit 256-mbit 8 4-gbit 512-mbit 9 8-gbit 1-gbit a 16-gbit 2-gbit 1 2 las h fa mily b = bottom parameter t = top parameter f 4 4 l v y b b 8 d 3 r package pinout indicator flash density scsp packages: y rd = scsp 0 = no die 4 = 256-mbit b = x16d ballout 6 0 0 parameter location product line designator 38f = stacked flash + xram combo product family lv = intel strataflash ? wireless memory system 0 = no die psram density 0 = no die 6 = 128-mbit voltage y = 1.8 volt core and i/o device details 0 = initial version of the product s i.e. for this specific example: speed (code die): y 90 ns aysnc/14 ns sync for 256-mbit flash @ 1.7 v - 2.0 v i/o y 85 ns aysnc/14 ns sync for 256-mbit flash @ 1.8 v - 2.0 v i/o flash process technology: 0.13 m etox? viii process flash #1 flash #2 ram #1 ram #2 flash family lead-free scsp packages: y pf = scsp f 48f = stacked flash only combo 58f = stacked flash / xram combo 3 = 128-mbit g = top-top parameter z = 1.8 volt core and 3 volt i/o speed (data die): y 170 ns aysnc/14 ns sync for flash @ 1.7 v - 2.0 v i/o .com .com .com .com 4 .com u datasheet

▲Up To Search▲

Price & Availability of RD38F4460LVY

	To Download RD38F4460LVY Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .